Part Number Hot Search : 
2600P 2008N DEVICE 201R0 3042DMA 2S161 DDC124EK M5106
Product Description
Full Text Search
 

To Download QL82SD-PT280 Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
  ? 2002 quicklogic corporation ?      ?      preliminary 1 www.quicklogic.com device highlights lvds serdes basic features  10 high speed bus lvds serial links? bandwidth up to 5 gbps  eight independent bus lvds serial transceivers with operating speeds to 632 mbps per channel  two independent bus lvds clock serial transceivers with operating speeds to 400 mhz per channel  integrated clock and data recovery (cdr) with no external analog components required  cdr bypass for applications with external clock source  programmable serial to parallel configuration  10-bit data width?with  clock recovery  4-bit, 7-bit and 8-bit data widths? with external clock  1-bit asynchronous level conversion  fast lock and random (auto) lock capable  lock signal feedback  i/o support for lvttl, lvcmos, pci, gtl+, sstl2, sstl3, lvds, lvpecl  low power/independent power-down mode for each serdes channel  ieee1149.1 jtag support & boundary scan  operation over pcb or backplane traces, or across twisted pair cabling up to 25 m  point-to-point, multi-point, and multi-drop support  pre-emphasis control on each lvds channel link extended features the following can be implemented into the programmable logic:  utopia level 2, 16-bit wide system interface (up to 50 mhz) with parity support for atm applications  utopia level 3 compatible 8-bit wide system interface (up to 100 mhz) with parity support for atm applications  csix-l1 32-bit switch fabric interface (up to 100 mhz)  supports generic 8,16,32-bit microprocessor bus interface for configuration, control and status monitoring  supports generic 32, 64-bit peripheral bus interface for bridging functions flexible programmable logic  2,016 programmable logic cells  536 k system gates  muxed architecture; non-volatile technology  completely customizable for any digital application dual port sram blocks  36 dual port sram blocks  configurable array sizes (by 2, 4, 9, 18)  < 3 ns access times, fifo capable of over 300 mhz  configurable as ram or fifo ql82sd device data sheet
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 2 programmable i/o  up to 252 programmable i/o pins  high performance enhanced i/o (eio): less than 3 ns tco  programmable slew rate control  programmable i/o standards  lvttl, lvcmos, pci, gtl+, sstl2, and sstl3, lvds, lvpecl  four independent i/o banks  three register configuration: input, output, oe embedded computational unit (ecu) blocks  integrated multiply, add, and accumulate function  18 distributed mac blocks  8 8 multiply (sign & unsigned)  16-bit carry add advanced clock network  nine global clock networks consisting of:  one dedicated  eight programmable  eight i/o (high drive) networks: two i/os per bank  ten quad-net networks ? five per quadrant figure 1: ql82sd device block diagram table 1: ql82sd device table customer part # serdes data lv d s clocks sram blocks logic cells ecu blocks programmable i/o ql82sd-pq208 4 2 36 2016 18 75 QL82SD-PT280 8 2 36 2016 18 121 ql82sd-ps484 8 2 36 2016 18 209 ql82sd-pb516 8 2 36 2016 18 252 ram blocks embedded computational units (ecus) ram blocks io block io block io block 2016 logic cells clkb ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 clka lvds/serdes io block io block
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 3 www.quicklogic.com general description lvds serdes transmitter and receiver a quicksd lvds serdes device in serializer mode takes a parallel data bus and a separate clock and converts them into a serial data stream. in deserializer mode, it takes a serial data stream and converts it to a configurable bit wide parallel data bus and separate clock. the reduced number of i/o board traces and cable connectors saves on cost and significantly simplifies design. skew and timing issues are significantly reduced and performance is enhanced. figure 2 and figure 3 illustrate the block diagrams of the quicksd device transmitter and receiver. figure 2: lvds serdes transmitter block diagram figure 3: lvds serdes receiver block diagram rl = 2 7 ? - 100 ? vo + vo - il = 8-12 ma do + do - 300 k 300 k /enable parallel to serial . . . . txd [9:0] ttl_din din + din - 300k w 300k w vcm = 0.2 v - 2.2 v serial to parallel . . . . fpga rxd [9:0]
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 4 lvds serdes applications the quicksd device is designed to address the need for high-speed serial communications. it maintains the features of standard discrete serdes devices, but integrates these features with customizable logic to allow for the highest degree of flexibility, performance, and integration at the lowest cost. the quicksd device is designed to support both transmit and receive requirements in a single chip. the device can support multiple channels in a variety of modes (with or without clock recovery,) a variety of translation widths (1:1 to 1:10), as well as a range of frequencies. these capabilities make this device ideal in applications where the performance is critical and customization is required. the quicksd device targets three applications: on-board, board-to-board (via common backplane), and box-to-box (via common cable). software support the turnkey quickworks ? package from quicklogic ? provides the most complete esp and fpga software solution from design entry to logic synthesis, to place and route, and to simulation. the package provides a solution for designers who use third-party tools from cadence, mentor, orcad, synopsys, viewlogic, veribest and other third-party tools for design entry, synthesis, or simulation. a power calculator is also provided for serdes power consumption. to speed up the quicksd design process, quicklogic includes a serdes wizard in its quickworks package. this wizard simplifies the process of configuring the multi-channel serdes core into each of its modes. for details on the serdes wizard, please refer to "the ql82sd quickstart design guide". to find this guide go to the quicksd device documentation web page at http://www.quicklogic.com/home.asp?pageid=315&smenuid=199#order . process data quicksd is fabricated on a 0.25 , five-layer metal cmos process. the core voltage is 2.5 volt v cc supply and 3.3 v tolerant i/o with the addition of 3.3 volt v ccio . quicksd is available in commercial and industrial temperature grades.
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 5 www.quicklogic.com ordering information maximum ratings and operating range table 2: absolute maximum electrical ratings v cc voltage -0.3 v to 4 v bus lvds driver output voltage -0.3 v to +2.8 v lvcmos/lvttl input voltage -0.3 v to (v cc + 0.3 v) bus lvds output short circuit duration 10 ms lvcmos/lvttl output voltage -0.3 v to (v cc + 0.3 v) esd rating hbm 2 kv bus lvds receiver input voltage -0.3 v to +2.8 v table 3: absolute maximum thermal ratings junction temperature +150 c lead temperature (soldering, 4 seconds) +260 c storage temperature -65 c to +150 c thermal and power dissipation characteristics see the following table table 4: thermal and power dissipation characteristics package 0 ja (*c/w vs. airflow 0 jc (*c/w) estimated maximum power dissipation (w) 0.0 0.5 1.0 2.0 pq208 26.0 24.5 23.0 22.0 11.0 1.65 ql 82sd - 4 pb516 c quicklogic device quicksd device part number sp eed grade 4 = quick 5 = fa st 6 = fa ste r 7 = fa ste st package code pq208 = 208-pin fpbga pt280 = 280-pin bga (1.0mm) ps484 = 484-pin bga (1.0mm) pb516 = 516-pin bga (1.27mm) operating range c = commercial i = industrial m = military
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 6 electrical specifications - lvds serdes lvds serdes transceiver capability (speed) general test conditions all tests are done for the 484-pin bga package (1.00 mm pitch). the tests are set up so that an lvds serdes channel of a ql82sd transmits, and the other lvds serdes channel of the same device (or another ql82sd device) receives. all results are given as worst cases over commercial temperature, vcc, and process, with pllvcc = 2.5 v unless otherwise specified. if the ql82sd device is used only for transmit or receive, but not both simultaneously, the performance can be significantly better, and, in many cases, exceeds 1 gb/s per channel. note: all data are in mb/s. low/high frequencey refers to internal serdes pll lock range (see table 29 on page 31 for more information). pt280 18.5 17.0 15.5 14.0 7.0 2.24 ps484 28.0 26.0 25.0 23.0 9.0 2.42 pb516 20.0 19.0 17.5 16.0 7.0 2.51 table 5: operating ranges symbol parameter industrial commercial unit min max min max vcc supply voltage 2.3 2.7 2.3 2.7 v vccio i/o input tolerance voltage 2.3 3.6 2.3 3.6 v t a ambient temperature -40 85 0 70 c k delay factor -4 speed grade 0.43 2.16 0.47 2.11 n/a -5 speed grade 0.43 1.80 0.46 1.76 n/a -6 speed grade 0.43 1.26 0.46 1.23 n/a -7 speed grade 0.43 1.14 0.46 1.11 n/a table 4: thermal and power dissipation characteristics package 0 ja (*c/w vs. airflow 0 jc (*c/w) estimated maximum power dissipation (w) 0.0 0.5 1.0 2.0
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 7 www.quicklogic.com cable - normal operation note: test conditions: up to 3-meter category 5 cable without any compensation. cable - high speed operation note: test conditions: up to 9" category 5 cable, and reference design in the programmable fabric portion of the device for internal skew compensation for channel link modes. backplane - normal operation note: test conditions: up to 18" point-to-point backplane without any compensation. table 6: cable - normal low frequency high frequency modes min max min max 10:1 mode not available 250 350 8:1 112 360 224 368 7:1 112 322 224 364 4:1 112 348 224 304 table 7: cable - high speed operation low frequency high frequency modes min max min max 10:1 mode not available 250 350 8:1 112 480 224 552 7:1 112 462 224 504 4:1 112 456 224 500 table 8: backplane - normal operation low frequency high frequency modes min max min max 10:1 mode not available 250 350 8:1 112 320 224 376 7:1 112 315 224 385 4:1 112 384 224 384
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 8 backplane - high speed operation note: test conditions: up to 18" point-to-point backplane, and reference design in the programmable fabric portion of the device for internal skew compensation for channel link modes. 1:1 mode (asynchronous level conversion) up to 9" cable: 0 to 500 mbps up to 18" point-to-point backplane: 0 to 700 mbps all numbers are for lvds channel performance only, and do not include the programmable fabric ? s ability to support high data rates. table 9: backplane - high speed operation low frequency high frequency modes min max min max 10:1 mode not available 250 350 8:1 112 632 224 632 7:1 112 630 224 630 4:1 112 628 224 628
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 9 www.quicklogic.com bus lvds dc specifications over the operating range, rxvcc = 3.0 v to 3.6 v. note: apply to pad_chx_p/n, pad_clkx_p/n figure 4: output differential voltage table 10: serializer / transmitter symbol parameter conditions min typ max units v od output differential voltage, pad_chx_p - pad_chx_n figure 4 figure 5 r l = 27 ? 240 325 420 mv v os offset voltage 0.90 1.10 1.30 v i os output short circuit current d o = 0 v, d in + h, en + oe + v cc 20 25 35 ma i oz tri-state output current d o = 0 v/v cc , en = 0 -25 10 25 a i ox power-off output current v cc - 0 v, d o = 0 v/v cc -25 10 25 a table 11: deserializer / receiver symbol parameter conditions min typ max units v th differential threshold high voltage figure 6 v cm = 1.1 v n/a 35 50 mv v tl differential threshold low voltage -50 -35 n/a mv i in input current v in = 0 v, v cc = 0 v / 3.6 v -25825a v in = 2.4 v, v cc = 0 v / 3.6 v -25 8 25 a d out + d out -
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 10 figure 5: output differential voltage for different loads figure 6: differential threshold voltages 82sd blvds output vod vs iod 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 8 9 10 11 12 13 iod ( m a ) vod ( v ) 100 ? 60 ? 27 ? 40 ? 80 ? vcm vth/ vtl
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 11 www.quicklogic.com supply current per channel note: more accurate supply current/power consumption numbers specific to your application should be calculated using the power calculator supplied with quicklogic ? s quickworks software package. table 12: serializer / transmitter symbol parameter conditions min typ max units i cct serializer supply current cl =10 pf figure 7 1:1 mode figure 7 ma figure 8 4:1 mode figure 8 ma figure 9 7:1 mode figure 9 ma figure 12 8:1 mode figure 12 ma figure 11 10:1 mode data/clock figure 11 ma i cctx serializer supply current powerdown en = 0 1 10 a table 13: deserializer / receiver symbol parameter conditions min typ max units i ccr serializer supply current cl = 10 pf figure 13 1:1 mode figure 13 ma figure 14 4:1 mode figure 14 ma figure 15 7:1 mode figure 15 ma figure 13 8:1 mode figure 13 ma figure 14 10:1 mode data/clock figure 14 ma i ccrx serializer supply current powerdown en = 0 1 10 a
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 12 figure 7: data/clock channel, 1:1 transmit mode figure 8: data/clock channel, 4:1 transmit mode figure 9: data/clock channel, 7:1 transmit mode figure 10: data/clock channel, 8:1 transmit mode figure 11: data/clock channel,10:1 transmit mode figure 12: data/clock channel, 1:1 receive mode s upp l y c urrent at v cc t x = 2 . 5 v icct (ma) clock frequency(mhz) 0 9 10 11 12 13 0 100 200 300 400 500 600 700 rt=100ohm rt= 27ohm supply current at vcctx = 2.5 v icct (ma) clock frequency(mhz) 10 15 20 20 40 60 80 100 120 140 160 rt=100ohm rt= 27ohm supply current at vcctx = 2.5v icct (ma) clock frequency(mhz) 10 10 30 50 70 90 rt=100ohm rt= 27ohm 15 20 25 supply current at vcctx = 2.5 v icct (ma) 10 20 40 60 15 20 25 rt=100ohm rt= 27ohm clock frequency(mhz) supply current at v cc r x = 3.3 v v cc = 2.5 v iccr (ma) clock fre q uenc y (mhz) 2 0 100 200 300 400 500 600 700 4 6 8 10 12 14 16 18 20 s upp l y c urren t a t v cc t x = 2 . 5 v icct (ma) clock frequency(mhz) 10 10 30 50 70 rt=100ohm rt= 27ohm 15 20 25
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 13 www.quicklogic.com figure 13: data/clock channel, 4:1 receive mode figure 14: data/clock channel, 7:1 receive mode figure 15: data/clock channel, 8:1 receive mode figure 16: data/clock channel, 10:1 receive mode iccr (ma) clock frequency (mhz) 5 20 40 60 80 100 120 140 160 15 20 25 supply current at v cc r x = 3.3 v, v cc = 2.5 v 10 iccr (ma) clock frequency (mhz) s upp l y current at v cc r x = 3 . 3 v, v cc = 2 . 5 v 0 10 30 50 70 90 20 10 5 15 iccr (ma) clock frequency (mhz) 10 20 30 40 50 60 70 80 90 5 s upp l y c urrent at v cc r x = 3 . 3 v , v cc = 2 . 5 v 20 15 10 0 iccr (ma) clock frequency (mhz) s upp l y c urrent at v cc r x = 3 . 3 v , v cc = 2 . 5 v 0 10 15 20 5 20 25 30 35 40 45 50 55 60 70
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 14 serdes timing requirements note: both table 14 and table 15 refer to cdr (10:1) mode for chx_txclk and channel link (8:1, 7:1, 4:1) mode for clkx_txclk figure 17: serializer transmit clock / deserializer reference clock transition times table 14: serializer / transmitter transmit clock symbol parameter conditions min typ max units t tcp transmit clock period mode dependent n/a t n/a ns t tdc transmit clock duty cycle 45 50 55 % t clkt transmit clock input transition time figure 17 1 n/a n/a v/ns t jit transmit clock input jitter n/a n/a 150.0 ps (rms) table 15: deserializer / receiver transmit clock symbol parameter conditions min typ max units t rfcp reference clock period mode dependent n/a t n/a ns t rfdc reference clock duty cycle 40 50 60 % t rfcp/ t tcp ratio of reference clock to transmit clock 0.4 0.5 0.6 n/a t rftt reference clock transition time figure 17 1 n/a n/a v/ns 90% 90% 10% 10% txclk tclkt/trftt tclkt/trftt
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 15 www.quicklogic.com serdes switching characteristics - serializer/transmitter ] table 16: serializer/transmitter switching characteristics cdr (10:1) mode symbol parameter conditions min typ max units t hzd pad_chx_p/n high to tri-state delay figure 18 1.9 2.2 2.5 ns t lzd pad_chx_p/n low to tri-state delay 1.9 2.0 2.2 ns t zhd pad_chx_p/n tri-state to high delay 1.9 2.4 3.0 ns t zld pad_chx_p/n tri-state to low delay 2.0 2.3 2.8 ns t dis chx_txd[9:0] setup to chx_txclk figure 19 2.6 3.2 ns t dih chx_txd[9:0] hold from chx_txclk 2.1 2.7 ns t pld serializer pll lock time figure 20 90 us channel link (8:1, 7:1, 4:1) mode symbol parameter conditions min typ max units t hzd pad_chx_p/n high to tri-state delay figure 18 1.9 2.2 2.5 ns t lzd pad_chx_p/n low to tri-state delay 1.9 2.0 2.2 ns t zhd pad_chx_p/n tri-state to high delay 1.9 2.4 3.0 ns t zld pad_chx_p/n tri-state to low delay 2.0 2.3 2.8 ns t dis chx_txd[n-1:0] setup to chx_txclk figure 21 2.6 3.2 ns t dih chx_txd[n-1:0] hold from chx_txclk 2.1 2.7 ns t sd serializer delay 1.7 ns t scp serial transmit clock period t/mode ns t txd[n-1] transmitter output pulse position for bit [n-1] [n-1] x t scp + 1.1 [n-1] x t scp + 1.5 ns t pld serializer pll lock time figure 20 90 us asynchronous level conversion (1:1) mode t hzd pad_chx_p/n high to tri-state delay figure 18 1.9 2.2 2.5 ns t lzd pad_chx_p/n low to tri-state delay 1.9 2.0 2.2 ns t zhd pad_chx_p/n tri-state to high delay 1.9 2.4 3.0 ns t zld pad_chx_p/n tri-state to low delay 2.0 2.3 2.8 ns t asd asynchronous serializer delay - data channel figure 22 1.8 ns t asc asynchronous serializer delay - channel clock 1.7 ns
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 16 figure 18: serializer delays to tri-state figure 19: 10:1 mode serializer transmit with embedded clock figure 20: serializer pll times 3v 0v v v 0h 0l en pad_p/n t lzd t hzd 50% t zhd t zld 50% 1.1v 50% 50% 50% 1.5v 1.5v 1.1v ch0_txclk ch0_txd[9:0] a b c d e dis dih t t f pad_ch0_p/n t zhd or t zld 0.8v t hzd or t lzd tri-state output active tri-state txclk pad_p/n enable 2.0v
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 17 www.quicklogic.com figure 21: channel link mode serializer transmit (using 8:1 mode as example) figure 22: 1:1 mode asynchronous level conversion mode serializer delays [bit3][bit2][bit1][bit0][bit7][bit6][bit5][bit4] pad_clkx _p/n pad_ chx _p/n txd [4] [5] [6] [7] [0] chx _ txd [7:0] chx _ txclk note: [n-1] physical positions wrt pad_clkx_p/n while pad_chx_p/n bit[n] bit positions wrt chx _ txd [7:0]. t t t t txd t txd t txd t txd t txd t dis dih sd denotes refers to bit logical ch0_txd [0] pad_ch0_p/n clka_txclk pad_clka_p/n t asd t asc
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 18 serdes switching characteristics - deserializer/receiver a. these values include the delay resulting from application of internal compensation for data/clock skew. table 17: deserializer / receiver switch characteristics cdr (10:1) mode symbol parameter conditions min typ max units t rcp chx_rxclk period 28.5 t 40.0 ns t rdc chx_rxclk duty cycle 45 50 55 % t dd deserializer delay figure 23 2 t rcp + 1.5 2 t rcp + 2.5 2 t rcp + 3.5 ns t rxpd chx_rxclk to chx_rxd[9..0] 1.5 2.5 3.5 ns t dsr1 deserializer pll lock time from powered-down state figure 24: 25 mhz figure 24: 50 mhz 5 8 us us t dsr2 deserializer pll lock time from syncpat figure : 25 mhz figure : 50 mhz 1 0.75 us us t djit pad_chx_p/n jitter 25 mhz 50 mhz 350 200 ps ps channel link (8:1, 7:1, 4:1) mode symbol parameter conditions min typ max units t rcp chx_rxclk period t ns t rdc chx_rxclk duty cycle 45 50 55 % t dd deserializer delay figure 26 2 t rcp + 1.5 2 t rcp + 2.5 2 t rcp + 3.5 ns t rxpd chx_rxclk to chx_rxd[n-1..0] 1.5 2.5 3.5 ns t rxds pad_chx_p/n setup to strobe position 150 200 ps t rxdh pad_chx_p/n hold to strobe position 150 200 ps t scd pad_clkx_p/n to serial clock delay a 0.6 0.8 1 ns t scp serial clock period t/mode ns t rxd[n-1] receiver input strobe position for bit [n-1] [n-1] t scp + 1.1 [n-1] t scp + 2.4 ns t dsr1 deserializer pll lock time from powered-down state figure 24: 25 mhz figure 24: 50 mhz 5 8 us us t djit pad_chx_p/n jitter 25 mhz 50 mhz 300 150 ps ps asynchronous level conversion (1:1) mode t add asynchronous deserializer delay - data channel figure 27 1.7 ns t adc asynchronous serializer delay - channel clock a 0.6 0.8 1 ns lvds link frequency compression mode -1 mode dependent lvds link frequency compression mode -1 mode dependent
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 19 www.quicklogic.com figure 23: 10:1 mode deserializer receive with embedded clock figure 24: deserializer pll lock time from power down figure 25: 10:1 mode deserializer pll lock time from syncpat rxpd dd t a b ch0_txclk ch0_rxd[9:0] ch0_rxclk pad_ch0_p/n t 2.0v enable chx_txclk pad_chx_p/n chx_lock chx-rxd [n-1,0] chx_rxclk oe t zhlk dsr1 t sync patterns zhr or zlr t t data t hzr or t lzr sync symbol or din0-9 1.5v 0.8v enable chx_txclk pad_chx_p/n chx_lock chx-rxd [n-1,0] chx_rxclk oe vcc dsr2 t sync patterns data zlr t t zhr or sync symbol or din0-9 t hzr or t lzr 0.0v 0.8v 1.2v 1.0v
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 20 figure 26: channel link mode deserializer receive (using 8:1 mode as example) figure 27: 1:1 mode asynchronous level conversion mode deserializer delays serdes bit error rate the following table indicates the serdes bit error rate at ta = 25 c and pllvcc = 2.5 v unless otherwise specified. table 18: serializer/deserializer bit error rate modes bit error rate 10:1 < 1 x 10 -12 8:1 < 1 x 10 -12 7:1 < 1 x 10 -12 4:1 < 1 x 10 -12 [bit3] [bit2] [bit1] [bit0] [bit7] [bit6] [bit5] [bit4] pad_ clkx _p/n pad_ chx_p/n serialclock (internal) rxd [1] max [0] max [1] min [0] min chx _ rxclk chx _ rxd [7:0] note: [n-1] denotes physical strobe positions wrt pad_clkx_p/n while pad_chx_p/n bit[n] refers logical bit positions wrt chx _ rxd [7:0]. t t t rxd t rxd t rxd t t t t rcp scp scd strobe rxds rxdh t t rxpd dd rxd t to ch0_txd [0] pad_ch0_p/n clka_txclk pad_clka_p/n t asd t asc
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 21 www.quicklogic.com electrical specification - programmable fabric dc characteristics dc input/output levels note: the above table gives the programmable logic timing model for the quicksd device. the programmable logic includes the following major elements: super logic (flip-flop and combinational circuit), clock, and i/o. table 19: dc characteristics symbol parameter conditions min max units i i i or i/o input leakage current v i = v ccio or gnd -10 10 a i oz 3-state output leakage current v i = v ccio or gnd -10 10 a c i input capacitance a a. capacitance is sample tested only. clock pins are 12 pf maximum. 8pf i os output short circuit current b b. only one output at a time. duration should not exceed 30 seconds. v o = gnd -15 -180 ma v o = v cc 40 210 ma i cc d.c. supply current c c. for -4/-5/-6/-7 commercial grade devices only. maximum icc is 3 ma for all industrial grade devices. v i, v o =v ccio or gnd 0.50 (typ) 2 ma i ccio d.c. supply current on v ccio 02ma i ref d.c. supply current on v ref -10 10 a i pd pad pull-down (programmable) v ccio = 3.6 v 150 a table 20: dc input/output levels v ref v il v ih v ol v oh i ol i oh v min v max v min v max v min v max v max v min ma ma lvttl n/a n/a - 0.3 0.8 2.0 v ccio - 0.3 0.40 2.40 2.0 - 2.0 lvcmos2 n/a n/a - 0.3 0.7 1.7 v ccio - 0.3 0.70 1.70 2.0 - 2.0 gtl+ 0.88 1.12 - 0.3 v ref - 2.0 v ref + 2.0 v ccio - 0.3 0.60 n/a 40 n/a pci n/a n/a - 0.3 0.30 v cc 0.50 v cc v ccio - 0.5 0.10 v cc 0.90 v cc 1.5 - 0.5 sstl2 1.15 1.35 - 0.3 v ref - 0.18 v ref + 0.18 v ccio + 0.3 0.74 1.76 7.6 - 7.6 sstl3 1.30 1.70 - 0.3 v ref - 0.20 v ref + 2.0 v ccio + 0.3 1.10 1.90 8.0 - 8.0
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 22 super logic (flip-flop and combinational circuit) ac characteristics at vcc = 2.5 v, ta = 25 o c (k = 1) figure 28: super logic cell flip-flop structure figure 29: combinational delay for logic cell table 21: logic cells symbol parameter condition propagation delay (ns) fanout = 1 t pd combinational delay a a. stated timing for worst case propagation delay over process variation at vcc = 2.5 v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. figure 29 0.257 t su setup time b b. these limits are derived from a representative selection of the slowest paths through the logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. figure 30 0.22 t h hold time 0 t clk clock to q delay figure 31 0.255 t cwhi clock high time figure 32 0.46 t cwlo clock low time 0.46 t set set delay figure 33 0.18 t reset reset delay 0.09 t sw set width 0.30 t rw reset width 0.30 reset clk d set q tpd input output
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 23 www.quicklogic.com figure 30: setup and hold time for flip-flop figure 31: delay from clock input to flip-flop q output figure 32: clock high and low time for flip-flop figure 33: timing requirements for flip-flop set and reset tsu th input (d) clk
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 24 clock ac characteristics at vcc = 2.5 v, ta = 25 o c (k = 1) figure 34: clock structure i/o ac characteristics at vcc = 2.5 v, ta = 25 o c (k = 1) figure 35: i/o structure table 22: clock performance clock performance global dedicated logic cells 1.51 ns 1.59 ns i/os 2.06 ns 1.73 ns skew 0.55 ns 0.14 ns table 23: input register cell symbol input register cell only parameter propagation delay (ns) t pgck global clock pin delay to quad net 1.34 t bgck global clock buffer delay (quad net to flip flop) 0.56 programmable clock hardware clock global clock buffer global clock pgck bgck t t
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 25 www.quicklogic.com figure 36: input register cell table 24: input register cell symbol input register cell only parameter propagation delay (ns) t isu input register setup time: the amount of time the synchronous input of the flip flop must be stable before the active clock edge. 3.12 t ih input register hold time: the amount of time the synchronous input of the flip flop must be stable after the active clock edge. 0 t iclk input register clock to q: the amount of time taken by the flip flop to output after the active clock edge. 1.08 t irst input register reset delay: the amount of time between when the flip flop is ? reset ? (low) and when q is consequently ? reset ? (low). 0.99 t iesu input register clock enable setup time: the amount of time ? enable ? must be stable before the active clock edge. 0.37 t ieh input register clock enable hold time: the amount of time ? enable ? must be stable after the active clock edge. 0 pad e r q d + - tin, tini tisu ticlk tsid
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 26 table 25: standard input delays figure 37: input register timing figure 38: output register cell symbol parameter propagation delay (ns) standard input delays to get the total input delay and this delay to tisu t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications 0.34 t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications 0.42 t sid (gtl+) gtl+ input delay: gunning transceiver logic 0.68 t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v 0.55 t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5v 0.607 r clk d q tisu tih ticlk tiesu tieh tirst e pad output register
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 27 www.quicklogic.com table 26: output register cell figure 39: output register cell timing electrical specification - ram block figure 40: ram module symbol parameter propagation delay (ns) output register cell only t outlh output delay low to high (10% of h) 0.40 t outhl output delay high to low (90% of h) 0.55 t pzh output delay tri-state to high (10% of z) 2.94 t pzl output delay tri-state to low (90% of z) 2.34 t phz output delay high to tri-state 3.07 t plz output delay low to tri-state 2.53 t co clock to out delay 3.15 (fast slew) 10.2(slow slew) l h l h toutlh touthl l h z tpzh l h z tpzl l h z tplz l h z tphz wa wd we wclk re rclk ra rd [9:0] [17:0] [9:0] [17:0] mode asyncrd [1:0]
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 28 ram cell synchronous write timing table 27: ram cell synchronous write timing figure 41: ram cell synchronous write timing symbol parameter propagation delay (ns) t swa wa setup time to wclk: the amount of time the write address must be stable before the active edge of the write clock 0.675 t hwa wa hold time to wclk: the amount of time the write address must be stable after the active edge of the write clock 0 t swd wd setup time to wclk: the amount of time the write data must be stable before the active edge of the write clock 0.654 t hwd wd hold time to wclk: the amount of time the write data must be stable after the active edge of the write clock 0 t swe we setup time to wclk: the amount of time the write enable must be stable before the active edge of the write clock 0.623 t hwe we hold time to wclk: the amount of time the write enable must be stable after the active edge of the write clock 0 t wcrd wclk to rd (wa=ra): the amount of time between the active write clock edge and the time when the data is available at rd 4.38 tswa tswd tswe thwa thwd thwe twcrd old data new data wclk wa wd we rd
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 29 www.quicklogic.com ram cell read timing table 28: ram cell synchronous and asynchronous read timing figure 42: ram cell synchronous and asynchronous read timing symbol parameter propagation delay (ns) ram cell synchronous read timing t sra ra setup time to rclk: the amount of time the read address must be stable before the active edge of the read clock 0.686 t hra ra hold time to rclk: the amount of time the read address must be stable after the active edge of the read clock 0 t sre re setup time to wclk: the amount of time the read enable must be stable before the active edge of the read clock 0.243 t hre re hold time to wclk: the amount of time the read enable must be stable after the active edge of the read clock 0 t rcrd rclk to rd: the amount of time between the active read clock edge and the time when the data is available at rd 4.38 ram cell asynchronous read timing r pdrd ra to rd: amount of time between when the read address is input and when the data is output 2.06 re rd rclk ra tsra thra tsre thre old data new data trcrd rpdrd
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 30 lvds serdes description lvds serdes applications the ql82sd device in the quicklogic quicksd esp (embedded standard product) device family provides a completely integrated configurable serializer/deserializer interface solution combined with 536 k system gates of customizable logic. this device provides a means to receive and transmit high-speed serial data and implement any proprietary high-speed serial link. the ql82sd device is a high performance serializer/deserializer chip. it can be combined with fifo buffer memory to build a complete serial link. the need for external fifos can be eliminated by configuring the available internal ram as two 256 x 36 fifos. the embedded serdes core is a full duplex design with a serialization section for transmission and a deserialization section for reception. the transmitter and receiver can be configured for level conversion (1:1), signals that transmit a clock signal with the data (1:4, 1:7, 1:8), or applications that require clock recovery (1:10). the embedded serdes core has a system interface that emulates a synchronous fifo for ease of use. fifos allow maximum sustained performance of 600 mb/s running a full duplex link. their function is to handle the asynchronous interface between the bus data rate and the different serial data rates, and handle phase and frequency differences inherent in serial links. internal fifos of 256 36 or 512 16 can be cascaded with external fifos to expand the buffering to the desired size. the ql82sd is a versatile part that allows the system designer to create proprietary or standardized serial links by taking advantage of some, or all, of the embedded features. it has a number of useful features for system designers of proprietary links with additions of embedded computational units and customizable i/o. lvds serdes block functional description the quicksd serdes consists of a physical layer for high-speed serial communications, handling all data translations, clocking and timing. the core is made up of eight data channels and two channel clocks. these blocks contain the circuitry necessary for all the data muxing and de-muxing, clock multiplication and division, clock and data phase alignment, and clock recovery and encoding. the core can be configured to support systems that transmit a separate clock signal or that have the clock embedded into the data stream and require clock recovery.
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 31 www.quicklogic.com lvds serdes data channel configuration a representation of the serdes data channel is shown in figure 43 . the device consists of eight identical data channels. figure 43: serdes channel 0 each serdes data channel can be operated independently. the data channels are transceivers, so they can either send or receive data on the serial lvds wire pair. the direction of transfer is selected with the chx_oe pin. if this pin is high, the channel is in transmit mode, if this pin is low, the channel is in receive mode. the data channel can be configured to deal with different parallel data widths and clocking mechanisms, table 29 shows the settings for the chx_mode[3:0] pins and the modes that they refer to. for the channel clock a/b modes, see ? lvds serdes channel clock configuration ? on page 32 for more details. if the data channel is not needed, then it can be powered down (to reduce overall device power) by tying the chx_en signal low. this signal must be held high for normal operation. for a detailed description of how to use the various modes of the data channel to transmit and receive data, see ? lvds serdes transmit and receive operation ? on page 33 . table 29: chx_mode[3:0] chx_mode[3] description bit [3] low frequency (1), high frequency (0) determines high or low frequency lock range for internal serdes pll. when this bit is set to ? 1 ? , the low frequency range is selected. when this bit is set to ? 0 ? , the high frequency range is selected. bit [2] in 10:1 mode, this bit must be set to ? 0 ? . in channel clock mode, the pin setting does not matter. bit [1] embedded clock mode (0), channel-clock (1) bit [0] clka (1), clkb (0) channel clock select ch0_rst ch0_lock ch0_en ch0_oe ch0_pre_emp ch0_mode[3:0] ch0_sync ch0_txclk ch0_rxclk ch0_txd[9:0] ch0_rxd[9:0] pad_ch0-p pad_ch0_n serdes channel 0
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 32 lvds serdes channel clock configuration there are two serdes channel clocks within the core. figure 44 shows a representation of the channel clock. each channel clock is identical. figure 44: serdes clk a each of the two serdes channel clocks can be configured independently. they can be configured to act as the transmit or receive clock for up to 8 serdes data channels (for serial links where the clock is provided as a separate lvds wire pair). alternatively, the channel clock can be configured as a simple bi-directional io pin, where the internal signals are cmos, but the external pin is lvds. in such a case, the i/o will act simply as a level converter. since the channel clock may act as a transmit or receive clock (or as an input or output signal in data mode), the direction of the channel clock must be selected with the clkx_oe pin. if this pin is high, then the channel clock is transmitting a clock (or acting as an output signal in data mode). if this pin is low, then the channel clock is receiving a clock (or acting as an input signal in data mode). when the channel clocks are used to act as the transmit or receive clock for one or more data channels, then four modes are available, using the clkx_mode[1:0] input. table 30 shows these modes. when a channel clock is configured with clkx_mode[1:0] equal to 01, 10, or 11, then any of the data channels can be configured to use that channel clock as its clock, by setting the data channel's chx_mode inputs to point to the correct channel clock. see the section , ? lvds serdes data channel configuration, ? on page 31 for more information. when the channel clock is configured with clkx_mode[1:0] equal to 00, the channel clock becomes a simple lvds-to-cmos level converter. when clkx_oe is high, the channel clock will be configured as an output, in which the data supplied on the clkx_txclk pin is converted to lvds and comes out on the pad_clkx_p and pad_clkx_n external ldvs signals asynchronously. when clkx_oe is low, the channel clock is configured as an lvds input, in which the lvds signal on pad_clkx_p and pad_clkx_n is converted to cmos levels and enters the device on the clkx_rxclk pin. table 30: clkx_mode[1:0] clkx_mode[1:0] mode 00 1:1 mode (no pll) 01 4:1 mode 10 7:1 mode 11 8:1 mode clka_oe clka_rxclk clka_pre_emp clka_en clka_mode[1:0] clka_txclk pad_clka_p pad_clka_n serdes clka
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 33 www.quicklogic.com any data channel can also be configured as a level translator. this is done by setting that data channel's chx_mode[3:0] input to point to a channel clock (a or b) which has also been configured in level translator mode. lvds serdes transmit and receive operation the serdes core can transmit and receive serial data across lvds wires in many different formats. this section describes each of the various transmit and receive formats. transmit 10-bit data with embedded clock the waveform in figure 19 , illustrates how 10-bit data can be transmitted serially on the differential lvds outputs. note: the pad_chx_p and pad_chx_n outputs in the diagram are representing the data changes which occur on a pair of lvds signals. when the serdes is in 10-bit mode, no separate clock signal is needed, since the clock is embedded within the serial data stream. in figure 19 , you will notice that at t dis the rising edge of chx_txclk registers the 10-bit data value b within the serdes core. after about one clock period of chx_txclk, the serialized data begins to appear on the lvds outputs (pad_chx_p and pad_chx_n) in the following sequence: 1. first, a logic 1 is transmitted, which is the start bit, and part of the data used to transmit the clock. 2. then each of the 10 bits of the data value b is transmitted in sequence. 3. finally, a logic 0 is transmitted, which is the stop bit (msb first). this stop bit is the remaining part of the embedded clock. note: by using a stop bit value of 0 and a start bit value of 1, there is always a guaranteed 0 to 1 transition in the bitstream (the end of one frame and the beginning of the next). because of this, the receiver is able to recover the embedded clock from the serial bit stream. the pertinent timing parameters shown in figure 19 are:  t dis is the setup time needed for the chx_txd bus relative to the chx_txclk clock  t dih is the hold time for the chx_txd relative to the chx_txclk clock receive 10-bit data with embedded clock in 10-bit mode, the clock is embedded in the serial data stream on the pad_chx_p and pad_chx_n lvds signal (shown in figure 23 ) as one signal, but actually is a pair of differential signals). when using the serdes data channel in 10-bit receive mode, a reference clock is needed which matches the parallel clock rate of the transmitter (shown in figure 23 as chx_txclk). there is no timing phase relationship between the reference clock and the received parallel clock (chx_rxclk), but the two clocks will have the same frequency. note: the serial data bits are transmitted with a 0 as a stop bit and a 1 as a start bit, and. the serdes block recovers the clock from this data stream, as shown with the chx_rxclk waveform ( figure 23 ). the parallel 10-bit data is also recovered and timed appropriately with the recovered clock. the pertinent timing parameters shown in figure 23 are:
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 34  t dd is the delay from the rising edge of the start bit in the serial bitstream to the rising edge of the recovered parallel clock  t rxpd is the propagation delay time provided for the recovered data with respect to the recovered clock. transmit 8-bit data with channel clock when the serdes is in 8-bit mode, it must be configured to use a channel clock. the waveforms shown in figure 21 show the parallel transmit clock provided by the user to the clock channel (clkx_txclk), and the converted channel clock on the lvds outputs of the channel clock (pad_clkx_p and pad_clkx_n). note: the output of the channel clock has the same period as the parallel transmit clock. this is done to frame the serial data transmitted on the pad_chx_p and pad_chx_n pins. the lvds channel clock (pad_clkx_p and pad_clkx_n) is multiplied up by the receiver to capture each bit of the transmitted data. the 8-bit data is converted to a simple serial bit stream. the pertinent timing parameters shown in figure 21 are:  t dis is the setup time needed on the parallel transmit data (chx_txd[7:0] with respect to the parallel transmit clock (clkx_txclk)  t dih is the hold time needed on the parallel transmit data (chx_txd[7:0] with respect to the parallel transmit clock (clkx_txclk)  t sd is the clock delay between the rising edge of the parallel transmit clock to the rising edge of the lvds channel clock  t txd[n-1] is the serial data physical bit position with respect to the lvds channel clock. note: t txd[n-1] denotes physical bit positions wrt pad_clkx_p/n while pad_chx_p/n bit[n] refers to logical bit positions wrt chx_txd[7:0]. receive 8-bit data with channel clock the serdes in 8-bit receive mode receives serial data on the pad_chx_p and pad_chx_n lvds input, and a clock on the pad_clkx_p and pad_clkx_n lvds input (see figure 26 ). the lvds input clock is multiplied by 8 within the serdes core to capture the 8 bits of data from the pad_chx_p and pad_chx_n serial bitstream. the parallelized data goes out on the chx_rxd internal 8-bit bus, and the re-timed parallel clock goes out on the clkx_rxclk pin. the pertinent timing parameters shown in this diagram are:  t dd is the delay between the first bit of the serial data showing up in the serial bit stream and the rising edge of the retimed parallel clock corresponding to the same data frame  t rxpd is the propagation delay time provided for the recovered data with respect to the recovered clock  t rxds is the setup time needed for the serial data on the pad_chx_p and pad_chx_n lvds inputs to the rising edge of the internal serial clock strobe  t rxdh is the hold time needed for the serial data on the pad_chx_p and pad_chx_n lvds inputs relative to the internal serial clock strobe
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 35 www.quicklogic.com  t scd is the delay between the rising edge of the lvds channel clock and the first rising edge of the multiplied internal serial clock corresponding to the same data frame.  t rxd[n-1] is the internal clock strobe positions with respect to the rising edge of the lvds channel clock note: t rxd[n-1] denotes physical strobe positions with respect to pad clkx_p/n while pad_chx_p/n bit[n] refers to logical bit positions with respect to chx_rxd[7:0] asynchronous level conversion mode for the data channel and channel clock when the serdes data channel chx_mode[3:0] pins are set to use a channel clock which is in level translator mode, then that data channel is also in level translator mode. in level translator mode, the data channel only converts the internal cmos signal to lvds (for output mode), or vice versa for input mode. when the data channel or channel clock is in this asynchronous signal translation mode, and configured as outputs (chx_oe or clkx_oe high) the output mode waveforms in figure 22 apply. when the data channel or channel clock is in this asynchronous signal translation mode, and configured as inputs (chx_oe or clkx_oe low) the input mode waveforms in figure 27 apply. programmable fabric description the quicksd device features an enhanced super logic cell with an additional d flip-flop register and associated control logic. this advanced architectural approach addresses today's highly register intensive designs. the quicksd logic supercell structure, shown in figure 45 , is similar to the .35 mm quicklogic logic cell with the addition of a second register. both registers share clk, set and reset inputs. the second register has a two-to-one multiplexer controlling its input. this register can be loaded from the nz output or directly from a dedicated input. note: the input "pp" is not an "input" in the classical sense. it can only be tied high or low using default links only and is used to select which path "nz" or "ps" is used as an input to the register. all other inputs can be connected not only to "tiehi" and "tielo" but to multiple routing channels as well. the complete logic cell consists of two 6-input and gates, four two-input and gates, seven two-to-one multiplexers, and two d flip-flops with asynchronous set and reset controls. the cell has a fan-in of 30 (including register control lines) and fits a wide range of functions with up to 17 simultaneous inputs. it has six outputs, of which four are combinatorial and two are registered. the high logic capacity and fan-in of the logic cell accommodate many user functions with a single level of logic delay while other architectures require two or more levels of delay.
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 36 figure 45: serdes logic cell ram block description general description the quicksd device includes multiple dual-port 2,304-bit ram modules for implementing ram and fifo functions. each module is user-configurable into four different block organizations. modules can also be cascaded horizontally to increase their effective width or vertically to increase their effective depth as shown in the following figure. the ram can also be configured as a modified harvard architecture, similar to those found in dsps. figure 46: serdes 2,304-bit ram module qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 mp ms d1 d2 e1 e2 np ns f1 f2 f3 f4 f5 f6 ps pp qc qr az oz qz nz q2z fz mode [1:0] wa [9:0] wd [17:0] we wclk rclk asyncrd ra [9:0] rd [17:0] re 2,304-bit module
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 37 www.quicklogic.com there are 36 ram blocks within the quicksd device, for a total of 82.9 kbits of ram. using two "mode" pins, designers can configure each module into 128 x 18 (mode 0), 256 x 9 (mode 1), 512 x 4 (mode 2), or 1024 x 2 blocks (mode 3). the blocks are also easily cascadable to increase their effective width and/or depth. see figure 47 for cascaded ram modules. figure 47: cascaded ram modules the ram modules are dual-port, with completely independent read and write ports and separate read and write clocks. the read ports support asynchronous and synchronous operation, while the write ports support synchronous operation. each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1,024 words. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read operation (asyncrd input low), or as a flow-through enable for asynchronous read operation (asyncrd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. a similar technique can be used to create depths greater than 512 words. in this case address signals higher than the ninth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher read address bits for the multiplexer select signals. the ram blocks can be loaded with data generated internally (typically for ram or fifo functions). the ram achieve 155 mhz performance for the lowest speed grade devices when using multiple blocks cascaded together. multiple accessing of memories the extremely fast ram can be used in designs that require multiple memory accessing. the ram achieves 280 mhz performance for the fastest speed grade and 155 mhz performance for the lowest speed grade devices when using multiple blocks cascaded together. write through of data is also possible with the quicklogic ram. wdata waddr wdata rdata raddr rdata ram module (2304 bits) ram module (2304 bits)
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 38 ecu block description ecu block general description traditional programmable logic architectures do not implement arithmetic functions efficiently or effectively. these functions require high logic cell usage while garnering only moderate performance results. by embedding a dynamically reconfigurable computational unit, the quicksd device can address various arithmetic functions efficiently and effectively providing for a robust dsp platform ? this approach offers greater performance than traditional programmable logic implementations. the ecu block is ideal for complex dsp, filtering, and algorithmic functions. the quicksd device architecture will allow functionality above and beyond that achievable using dsp processors or programmable logic devices. the embedded block is implemented at the transistor level with the following block diagram. figure 48: serdes ecu block diagram ecu mode select the ecu block can be configured for eight arithmetic functions via an instruction as shown in table 31 . the modes for the ecu block are dynamically re-programmable through the instruction set sequencer. table 31: instruction set sequencer instruction set operation 0 0 0 multiply 0 0 1 multiply - add 0 1 0 accumulate 0 1 1 add 1 0 0 multiply (registered) a a. a[15:0] set to zero. 1 0 1 multiply - add (registered) 1 1 0 multiply accumulate 1 1 1 add (registered) abus 16 xbus 8 ybus 8 ibus 3 sign 1 rbus 17 88 16 16 multiply add register sequencer memory logic cell
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 39 www.quicklogic.com clock networks description global clocks in the quicksd device, there are nine global clock networks: one is dedicated and eight are programmable . global clocks can drive logic cell, i/o, ecu blocks and ram registers in the device. five global clocks will have access to a quad net (local clock network) connection with a programmable connection to the register inputs. figure 49 gives the global clock methodology figure 49: global clock quad-net network there are five quad-net local clock networks in each quadrant for a total of 20 in a device. each quad-net is local to a quadrant. quad-net is multiplexed with the clock buffer before driving the column clock buffers.
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 40 dedicated clock there is one dedicated clock in quicksd devices. it connects to the clock input of the supercell, i/o, and ram registers through a hardwired connection and is multiplexed with the programmable clock input. there are four inversions from pad to register inputs and the dedicated clock takes on the same configuration as the global clock. the dedicated clock provides a fast global network with low skew. you can select either the dedicated clock or the programmable clock; figure 50 gives the dedicated clock circuitry within the logic cell. figure 50: dedicated clock circuitry the performance of the dedicated clock is given in table 32 table 32: dedicated clock performance clock performance tt, 25c, 2.5 v global dedicated macro (rear) 1.51 1.59 i/o (far) 2.06 1.73 skew 0.55 0.14 programmable clock hard-wired clock clk
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 41 www.quicklogic.com i/o cell structure i/o cell structure general description the quicksd device features a variety of distinct i/o pins to maximize performance, functionality, and flexibility with bi-directional i/o pins and input-only pins. all input and i/o pins are 2.5 v and 3.3 v tolerant and comply with the specific i/o standard selected. the outputs swing from vss to vccio (0 v to 3.3 v 10%). the vccio pins must be tied to a 3.3 v supply to provide 3.3 v compliance. if 3.3 v compliance is not required, then these pins must be tied to the 2.5 v supply. table 33 summarizes the i/o specifications that are supported. as designs become more complex and requirements more stringent, varying i/o standards are developing for specific applications. i/o standards for processors, memories and various bus applications have become common place and a requirement for many systems. in addition, i/o timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. the quicksd device has addressed these changing system requirements. the quicksd device includes a completely new i/o cell which consists of programmable i/os as well as a new cell structure consisting of three registers: input, output and output enable. the quicksd device offers banks of programmable i/o that addresses many of the new bus standards that are popular today. in addition, the input register addresses the setup time, the output register addresses clock-to-out time, and the oe register addresses the switching time from high impedance to a given value. figure 51 shows the quicksd device i/o cell. table 33: supported i/o specifications /o standard reference voltage output voltage application lvttl n/a 3.3 general purpose lvcmos2 n/a 2.5 general purpose pci n/a 3.3 pci bus applications gtl+ 1 n/a high speed bus - pentium pro sstl3 1.5 3.3 memory bus - hitachi, ibm sstl2 1.25 2.5 memory bus - hitachi, ibm
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 42 figure 51: quicksd i/o cell the bi-directional i/o pin options can be programmed for input, output, or bi-directional operation. each bi-directional i/o pin is associated with an i/o cell which features an input/feedback register, an input buffer, output/feedback register, three-state output buffer, an output enable register, and two 2-to-1 multiplexers. for input functions, i/o pins can provide combinatorial registered data or both options simultaneously to the logic array. for combinatorial input operation, data is routed from i/o pins through the input buffer to the array logic. for registered input operation, i/o pins drive the d input of input cell registers, allowing data to be captured with fast set-up times without consuming internal logic cell resources. for output functions, i/o pins can receive combinatorial or registered data from the logic array. for combinatorial output operation, data is routed from the logic array through a multiplexer to the i/o pin. for registered output operation, the array logic drives the d input of the output cell register which in turn drives the i/o pin through a multiplexer. the multiplexer allows either a combinatorial or a registered signal to be driven to the i/o pin. the three-state output buffer controls the flow of data from the array logic to the i/o pin and allows the i/o pin to act as an input and/or output. the buffer's output enable can be individually controlled by a logic cell array or any pin (through the regular routing resources), or bank-controlled through one of the global networks. the signal can also be either combinatorial or registered. this is identical to that of the flow for the output cell. for combinatorial control operation, data is routed from the logic array through a multiplexer to the three-state control. for registered control operation, the array logic drives the d input of the oe cell register which in turn drives the three-state control through a multiplexer. the multiplexer allows either a combinatorial or a registered signal to be driven to the three-state control. for output functions, i/o pins can be individually configured for active high, active low, or open-drain inverting operation. in the active high and active low modes, the pins of all devices are fully 3.3 v compliant. e q r d e d r q pa d e d r q + -
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 43 www.quicklogic.com when i/o pins are unused, the oe controls can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. i/o cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global networks, or from two input pins per bank of i/o's. the clk and reset signals share a common line, while the clock enables for each register can be independently controlled. additionally, the output and enable registers will increase a device's register count. the addition of an output register will also decrease the tco. since the output register does not need to drive the routing, the length of the output path is also reduced. extra registers add more inputs and outputs to the i/o structure. extra routing resources are added to connect the i/o structure to the other parts of the device. i/o interface support is programmable on a per bank basis. there are 4 i/o banks per chip. users can not mix a 2.5 volt i/o with 3.3 volt i/o on the same i/o bank. figure 52 illustrates the multiple i/o bank configurations. figure 52: multiple i/o bank configurations each i/o bank is independent of other i/o banks and each i/o bank has its own v ccio and v ref supplies. a mixture of different i/o standards can be used on the device; however, there is a limitation as to which i/o standards can be supported within a given bank. differential i/o can be shared with non differential i/o. there can only be one v ref and one v ccio per bank. programmable slew rate each i/o has programmable slew rate capability. the rate is programmable to one of two slew rates: either fast or slow. the slower rate can be used to reduce ground bounce noise. the slow slew rate is 1 v/ns under typical conditions. the fast slew rate is 2.8 v/ns table 34: 3.3 v slew rate vccio = 3.3 v fast slew slow slew rising edge 2.8 v/ns 1.0 v/vs falling edge 2.86 v/ns 1.0 v/ns vccio 0 vref 0 i/o bank 0 i/o bank 1 vccio 1 vref 1 i/o bank 2 vccio 2 vref 2 i/o bank 3 vccio 3 vref 3
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 44 . note: condition: 2.5 v, 25 c programmable weak-pull programmable weak pull-down resistors are available on each i/o. i/o weak pull-down eliminates the need for an external pull-down resistor for used i/o. the spec for pull-down current is a maximum of 150 ua under a worst case condition. - 148 ua @ 3.6 v, - 55 c, - 69 ua@ 2.5 v, 25 c. figure 53 illustrates the weak pull-down circuit. figure 53: i/o weak pull-down circuit i/o control and local hi-drives each bank of i/os has two input-only pins that can be programmed to drive the rst, clk, and en inputs of i/o's in that bank. these input-only pins also double up as high-drive inputs to a quadrant. both as an i/o control or high-drive, these buffers can be driven by the internal logic. the i/o control network and local high-drive performance is indicated in table 36 . table 35: 2.5 v slew rate vccio = 2.5 v fast slew slow slew rising edge 1.7 v/ns 0.6 v/vs falling edge 1.9 v/ns 0.6 v/ns table 36: i/o control network/ local hi-drive performance tt, 25c, 2.5v from pad from array i/o (slow) 1.00 ns 1.14 ns i/o (fast) 0.63 ns 0.78 ns skew 0.37 ns 0.36 ns i/o register 1 pa d
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 45 www.quicklogic.com programmable logic routing the ql82sd device provides six types of routing resources (as in the quickram devices): short (sometimes called segmented) wires, dual wires, quad wires, express wires, distributed networks, and defaults.  short wires span the length of one logic cell, always in the vertical direction. dual wires run horizontally and span the length of two logic cells. note: short and dual wires are predominantly used for local connections. they effectively traverse one or two logic cells that utilize an interconnect element to continue to the next cell or to change direction.  quad wires have passive link interconnect elements every fourth logic cell. as a result, these wires are typically used to implement intermediate or medium length fan-out nets.  express lines run the length of the programmable logic uninterrupted. each of these lines has a higher capacitance than a quad, dual or short wire, but less capacitance than shorter wires connected to run the length of the device. the resistance will also be lower because the express wires don't require the use of "pass" links. express wires provide higher performance for long routes or high fan-out nets.  distributed networks are described in the clock/control section. these wires span the programmable logic, and are driven by "column clock" buffers. each dedicated clock network pin buffer is hard wired to a set of column clock buffers. five global networks "global buffers" can be connected through special purpose routing called "hsck lines" to either a dedicated pin buffer, or any vertical routing wire crossing it. global por (power-on reset) the quicksd device features a global power-on reset. this reset will be hardwired to all registers and will reset the registers upon power-up of the device. the circuitry used to support the global por is similar to the power-up loading circuitry. figure 54: power-on reset separate power & logic cell power to decrease the logic cell area and to eliminate the need for disable transistors in the input stage of the logic cell, a separate power supply for the logic cells has been added to the quicksd device. this supply will be grounded during programming and for various test modes. vcc power-on reset q 0
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 46 ieee standard 1149.1a the quicksd device supports ieee standard 1149.1a. the following public instructions are supported: bypass, extest, and sample/preload. two additional modes ramwt and ramrd can be used to load the ram. figure 55: jtag block diagram jtag bsdl support  bsdl-boundary scan description language  machine-readable data for test equipment to generate testing vectors and software  bsdl files available for all device/ package combinations from quicklogic  extensive industry support available and atg (automatic test-vector generation) security fuses there are two security links, one to disable reading from the array and the other to disable jtag. 8-bit programming the quicksd device has 8-bit programming capability. the addition of four extra programming supplies is used in the reduction of programming time. tck tms trstb logic cell array i/o registers user defined data register bypass register boundary-scan register (data register) mux instruction register mux tap controller state machine (16 states) instruction decode & control logic rdi tdo
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 47 www.quicklogic.com pin type description general pins table 37: general pin descriptions type description in input. a standard input-only signal out totem pole output. a standard active output driver t/s tri-state. a bi-directional, tri-state input/output pin table 38: general pin/bus descriptions pin/bus name type function vcc in supply pin. tie to 2.5 v supply. vccio in supply pin for i/o. set to 2.5 v for 2.5 v i/o, 3.3 v for 3.3 v compliant i/o, or refer to the i/o standards table. inref in differential i/o reference voltage, refer to differential voltage table. connect to gnd when using ttl, pci or lvcmos vccrec in lvds receiver vcc supply. connect to 3.3 v vccpll in pll vcc supply. connect to 2.5 v ioctrl in low skew i/o control pins. tie to gnd if unused gndpll in tie to gnd clk/pllin in programmable global clock pin or programmable pll input. tie to vcc or gnd if unused clk/dedclk/pllin in dedicated global clock pin or programmable pll input. pllout out programmable pll output pllrst in programmable pll reset. tie to vcc if the pll is unused. gnd in ground pin. tie to gnd on the pcb. t/gnd in thermal ground. used to dissipate heat from the device. tie to gnd on the pcb. i/o t/s programmable input/output/tri-state/bi-directional pin. clk in programmable global clock pin. tie to vcc or gnd if unused. tdi in jtag data in. tie to vcc if unused. tdo out jtag data out. leave unconnected if unused. tck in jtag clock. tie to gnd if unused. tms in jtag test mode select. tie to vcc if unused. trstb in jtag reset. tie to gnd if unused. nc out must be isolated and floating at all times
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 48 lvds serdes external signals lvds serdes internal signals (data channels 0 to 7) note: all ch0 signals above repeat for ch1-ch7. the eight serdes data channels 0 through 7 are identical. table 39: lvds serdes external signals signal name description ch0p, ch0n lvds signal pair for data channel 0 ch1p, ch1n lvds signal pair for data channel 1 ch2p, ch2n lvds signal pair for data channel 2 ch3p, ch3n lvds signal pair for data channel 3 ch4p, ch4n lvds signal pair for data channel 4 ch5p, ch5n lvds signal pair for data channel 5 ch6p, ch6n lvds signal pair for data channel 6 ch7p, ch7n lvds signal pair for data channel 7 clkap, clkan lvds signal pair for channel clock a clkbp, clkbn lvds signal pair for channel clock b table 40: lvds serdes internal signals (data channels 0 to 7) signal name description ch0_rst channel 0 reset signal ch0_oe channel 0 output enable (1=transmit, 0=receive) ch0_en channel 0 enable (reduces power when set to 0) ch0_mode[3:0] channel 0 mode pins. see the serdes data channel functional description ch0_txd[9:0] channel 0 parallel transmit data bus ch0_txclk channel 0 transmit/reference clock ch0_sync channel 0 sync control. when low, a sync pattern is generated on the ch0_data pins to provide a high-speed lock mechanism when using the embedded clock mode. when high, it will send the data in chx_txd. ch0_rxd[9:0] channel 0 parallel receive data bus ch0_rxclk channel 0 receive clock ch0_lock channel 0 lock indicator, to indicate when the serdes is locked to the serial bitstream, when using the embedded clock mode. ch0_pre_emp channel 0 pre-emphasis signal. when high, lvds transmitter boosts dynamic current during signal transitions.
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 49 www.quicklogic.com lvds serdes internal signals (channel clocks a and b) note: all clka signals above repeat for clkb. serdes channel clocks a and b are identical. 208 pqfp pinout diagram figure 56: ql82sd - 208pqfp pinout diagram table 41: lvds serdes internal signals (channel clocks a and b) signal name description clka_rst channel clock a reset signal clka_oe channel clock a output enable (1 =transmit, 0=receive) clka_en channel clock a enable (reduces power when set to 0) clka_mode[1:0] channel clock a mode pins. see the serdes channel clock functional description clka_txclk channel clock a parallel transmit clock clka_rxclk channel clock a parallel receive clock quicksd ql82sd-6pq208c pin #1 pin #53 pin #105 pin #157
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 50 208 pqfp pinout table table 42: 208 pqfp pinout table pin function pin function pin function pin function pin function 1 vccpll 43 vccpll 85 inref(a) 127 gnd 169 io(d) 2 gndpll 44 gndpll 86 ioctrl(a) 128 clk(5) 170 vccio(d) 3 vcc 45 gnd 87 vcc 129 clk(6) 171 vcc 4 gnd 46 ch7n 88 io(a) 130 clk(7) 172 io(d) 5 ch0n 47 ch7p 89 io(a) 131 clk(8) 173 io(d) 6 ch0p 48 gnd 90 vccio(a) 132 tms 174 io(d) 7 gnd 49 vcc 91 io(a) 133 gnd 175 ioctrl(d) 8 vcc 50 gnd 92 io(a) 134 io(c) 176 inref(d) 9 gnd 51 vccrec 93 io(a) 135 io(c) 177 ioctrl(d) 10 vccrec 52 vcc 94 io(a) 136 io(c) 178 io(d) 11 vccpll 53 gnd 95 gnd 137 io(c) 179 io(d) 12 gndpll 54 vcc 96 io(a) 138 vcc 180 io(d) 13 vcc 55 gnd 97 io(a) 139 io(c) 181 io(d) 14 gnd 56 vcc 98 io(b) 140 vccio(c) 182 vccio(d) 15 ch1n 57 trstb 99 io(b) 141 io(c) 183 io(d) 16 ch1p 58 clk(2) 100 io(b) 142 vcc 184 io(d) 17 vcc 59 clk(3)plli n(1) 101 io(b) 143 io(c) 185 vcc 18 gnd 60 clk(4)ded clk, pllin(0) 102 pllout(0) 144 ioctrl(c) 186 gnd 19 vccrec 61 io(a) 103 gndpll(1) 145 inref(c) 187 io(d) 20 gnd 62 io(a) 104 gnd 146 gnd 188 io(d) 21 vcc 63 io(a) 105 pllrst(1) 147 ioctrl(c) 189 io(d) 22 gnd 64 io(a) 106 vccpll(1) 148 io(c) 190 io(d) 23 gnd 65 vcc 107 vccio(b) 149 io(c) 191 vcc 24 clkan 66 gnd 108 io(b) 150 io(c) 192 vccio(d) 25 clkap 67 vccio(a) 109 gnd 151 vcc 193 io(d) 26 vcc 68 io(a) 110 io(b) 152 io(c) 194 io(d) 27 clkbn 69 io(a) 111 io(b) 153 gnd 195 gnd 28 clkbp 70 vcc 112 vcc 154 vccio(c) 196 io(d) 29 gnd 71 io(a) 113 io(b) 155 pllout(1) 197 io(d) 30 vccrec 72 io(a) 114 io(b) 156 gndpll(0 ) 198 vcc 31 vcc 73 io(a) 115 io(b) 157 gnd 199 clk(0) 32 gnd 74 io(a) 116 io(b) 158 pllrst(0) 200 clk(1) 33 gnd 75 io(a) 117 ioctrl(b) 159 vccpll(0) 201 tck 34 vccpll 76 io(a) 118 inref(b) 160 io(c) 202 vcc 35 gndpll 77 io(a) 119 ioctrl(b) 161 io(c) 203 tdi 36 ch6n 78 io(a) 120 gnd 162 io(c) 204 gnd 37 ch6p 79 vccio(a) 121 io(b) 163 io(d) 205 vcc 38 gnd 80 vcc 122 vccio(b) 164 io(d) 206 gnd 39 vcc 81 io(a) 123 io(b) 165 io(d) 207 tdo 40 gnd 82 gnd 124 vcc 166 io(d) 208 gnd 41 vccrec 83 io(a) 125 io(b) 167 gnd 42 vcc 84 ioctrl(a) 126 vcc 168 io(d)
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 51 www.quicklogic.com 280 fpbga pinout diagram figure 57: ql82sd - 280 fpbga top view figure 58: ql82sd - 280 fpbga bottom view quicksd ql82sd-6pt280c a b c d e f g h j k l m n p r t u v w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 pin a1 corner
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 52 280 fpbga pinout table table 43: 280 fpbga pinout table pin function pin function pin function pin function pin function pin function a1 pllout(1) c10 clk(8) e19 io(b) k16 io(a) r4 vcc u13 vccpll a2 io(c) c11 vccio(b) f1 io(d) k17 io(a) r5 vcc u14 gndpll a3 io(c) c12 io(b) f2 io(d) k18 inref(a) r6 vcc u15 vccpll a4 io(c) c13 io(b) f3 io(d) k19 ioctrl(a) r7 vcc u16 gndpll a5 inref(c) c14 io(b) f4 io(d) l1 io(d) r8 vcc u17 vccpll a6 ioctrl(c) c15 vccio(b) f5 gnd l2 io(d) r9 vcc u18 gndpll a7 io(c) c16 io(b) f15 vcc l3 io(d) r10 vcc u19 vccrec a8 io(c) c17 vccpll(1) f16 io(a) l4 io(d) r11 vcc v1 vccrec a9 io(c) c18 gndpll(1) f17 io(a) l5 vcc r12 vcc v2 vccrec a10 clk(7) c19 pllout(0) f18 io(a) l15 gnd r13 vcc v3 vccrec a11 io(b) d1 io(c) f19 io(b) l16 io(a) r14 vcc v4 vccrec a12 io(b) d2 io(c) g1 io(d) l17 io(a) r15 vcc v5 vccrec a13 ioctrl(b) d3 vccpll(0) g2 io(d) l18 io(a) r16 clk(2) v6 vccrec a14 ioctrl(b) d4 io(c) g3 io(d) l19 io(a) r17 trstb v7 vccrec a15 io(b) d5 io(c) g4 io(d) m1 io(d) r18 io(a) v8 vccrec a16 io(b) d6 io(c) g5 vcc m2 io(d) r19 io(a) v9 vccrec a17 io(b) d7 io(c) g15 vcc m3 vccio(d) t1 io(d) v10 vccrec a18 io(b) d8 io(c) g16 io(a) m4 io(d) t2 gnd v11 vccrec a19 io(b) d9 io(c) g17 io(a) m5 vcc t3 gnd v12 vccrec b1 pllrst(0) d10 io(c) g18 io(a) m15 vcc t4 gnd v13 vccrec b2 io(c) d11 clk(6) g19 io(a) m16 io(a) t5 gnd v14 vccrec b3 io(c) d12 io(b) h1 io(d) m17 vccio(a) t6 gnd v15 vccrec b4 io(c) d13 io(b) h2 io(d) m18 io(a) t7 gnd v16 vccrec b5 ioctrl(c) d14 io(b) h3 io(d) m19 io(a) t8 gnd v17 vccrec b6 io(c) d15 io(b) h4 io(d) n1 io(d) t9 gnd v18 vccrec b7 io(c) d16 io(b) h5 vcc n2 clk(0) t10 gnd v19 ch7p b8 io(c) d17 io(b) h15 vcc n3 io(d) t11 gnd w1 ch0n b9 tms d18 io(b) h16 io(a) n4 io(d) t12 gnd w2 ch0p b10 clk(5) d19 io(b) h17 io(a) n5 vcc t13 gnd w3 ch1n b11 io(b) e1 io(c) h18 io(a) n15 vcc t14 gnd w4 ch1p b12 io(b) e2 io(c) h19 io(a) n16 io(a) t15 gnd w5 ch2n b13 io(b) e3 vccio(d) j1 ioctrl(d) n17 io(a) t16 gnd w6 ch2p b14 inref(b) e4 io(d) j2 inref(d) n18 io(a) t17 gnd w7 ch3n b15 io(b) e5 gnd j3 vccio(d) n19 io(a) t18 io(a) w8 ch3p b16 io(b) e6 vcc j4 io(d) p1 io(d) t19 io(a) w9 clkan b17 io(b) e7 vcc j5 gnd p2 tck u1 tdo w10 clkap b18 pllrst(1) e8 vcc j15 vcc p3 io(d) u2 vccpll w11 clkbn b19 gnd e9 vcc j16 io(a) p4 io(d) u3 gndpll w12 clkbp c1 io(c) e10 gnd j17 vccio(a) p5 vcc u4 vccpll w13 ch4n c2 gnd e11 gnd j18 io(a) p15 gnd u5 gndpll w14 ch4p c3 gndpll(0) e12 vcc j19 ioctrl(a) p16 clk(4) dedclk, pllin(0) u6 vccpll w15 ch5n c4 io(c) e13 vcc k1 io(d) p17 clk(3) pllin(1) u7 gndpll w16 ch5p c5 vccio(c) e14 gnd k2 ioctrl(d) p18 io(a) u8 vccpll w17 ch6n c6 io(c) e15 gnd k3 io(d) p19 io(a) u9 gndpll w18 ch6p c7 io(c) e16 io(a) k4 io(d) r1 io(d) u10 nc w19 ch7n c8 io(c) e17 vccio(a) k5 gnd r2 tdi u11 vccpll c9 vccio(c) e18 io(b) k15 gnd r3 clk(1) u12 gndpll
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 53 www.quicklogic.com 484 pbga pinout diagram figure 59: ql82sd - 484pbga top view figure 60: ql82sd - 484pbga bottom view quicksd ql82sd-6ps484c a b c d e f g h j k l m n p r t u v w y aa ab 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 pin a1 corner
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 54 484 pbga pinout table table 44: 484 pbga pinout table pin function pin function pin function pin function pin function pin function a1 gnd d17 i/o h11 vcc m5 gnd r21 i/o w15 i/o a2 nc d18 i/o h12 gnd m6 vcc r22 i/o w16 i/o a3 i/o d19 vccpll<0> h13 vcc m7 vcc t1 ch5n w17 nc a4 i/o d20 i/o h14 vcc m8 vcc t2 vccrec w18 i/o a5 i/o d21 i/o h15 gnd m9 vcc t3 vccrec w19 i/o a6 i/o d22 i/o h16 nc m10 gnd t4 vccpll w20 i/o a7 i/o e1 ch1p h17 nc m11 gnd t5 gnd w21 i/o a8 i/o e2 vccrec h18 i/o m12 gnd t6 vcc w22 i/o a9 i/o e3 vccrec h19 i/o m13 gnd t7 gnd y1 ch7n a10 i/o e4 gndpll h20 i/o m14 gnd t8 nc y2 vccrec a11 i/o e5 gnd h21 i/o m15 gnd t9 nc y3 gnd a12 ioctrl e6 nc h22 i/o m16 gnd t10 nc y4 nc a13 i/o e7 nc j1 ch3p m17 i/o t11 gnd y5 i/o a14 i/o e8 clk<1> j2 vccrec m18 i/o t12 nc y6 i/o a15 i/o e9 i/o j3 vccrec m19 i/o t13 nc y7 i/o a16 i/o e10 i/o j4 gndpll m20 clk<7> t14 nc y8 i/o a17 i/o e11 nc j5 gnd m21 clk<5>/pll in<3> t15 nc y9 i/o a18 i/o e12 i/o j6 vcc m22 tms t16 gnd y10 i/o a19 i/o e13 i/o j7 vcc n1 clkbp t17 i/o y11 i/o a20 gnd e14 i/o j8 vcc n2 vccrec t18 i/o y12 ioctrl a21 pllout<1> e15 i/o j9 gnd n3 vccrec t19 i/o y13 ioctrl a22 i/o e16 i/o j10 vcc n4 gndpll t20 i/o y14 i/o b1 ch0n e17 i/o j11 vcc n5 gnd t21 ioctrl y15 i/o b2 gnd e18 i/o j12 gnd n6 vcc t22 i/o y16 i/o b3 tdo e19 i/o j13 vcc n7 vcc u1 ch5p y17 i/o b4 gnd e20 i/o j14 gnd n8 vcc u2 vccrec y18 i/o b5 i/o e21 i/o j15 vcc n9 vcc u3 vccrec y19 pllout<0> b6 i/o e22 i/o j16 nc n10 gnd u4 gndpll y20 pllrst<1> b7 tdi f1 ch2n j17 vccio n11 gnd u5 gnd y21 i/o b8 i/o f2 vccrec j18 i/o n12 gnd u6 vcc y22 i/o b9 i/o f3 vccrec j19 i/o n13 gnd u7 vccio aa1 ch7p b10 i/o f4 vccpll j20 i/o n14 vcc u8 i/o aa2 gnd b11 i/o f5 gnd j21 i/o n15 vcc u9 vccio aa3 gnd b12 i/o f6 vcc j22 i/o n16 i/o u10 nc aa4 i/o b13 ioctrl f7 vccio k1 clkan n17 vccio u11 vccio aa5 i/o b14 i/o f8 nc k2 vccrec n18 i/o u12 vccio aa6 i/o b15 i/o f9 vccio k3 vccrec n19 i/o u13 nc aa7 i/o b16 i/o f10 i/o k4 vccpll n20 i/o u14 vccio aa8 i/o b17 i/o f11 vccio k5 gnd n21 i/o u15 nc aa9 i/o b18 i/o f12 vccio k6 vcc n22 i/o u16 vccio aa10 i/o b19 pllrst<0> f13 i/o k7 vcc p1 ch4n u17 vccio aa11 i/o b20 i/o f14 vccio k8 vcc p2 vccrec u18 i/o aa12 inref b21 i/o f15 i/o k9 vcc p3 vccrec u19 i/o aa13 i/o b22 i/o f16 vccio k10 gnd p4 vccpll u20 ioctrl aa14 i/o c1 ch0p f17 i/o k11 gnd p5 gnd u21 i/o aa15 i/o c2 vccrec f18 i/o k12 gnd p6 vcc u22 inref aa16 i/o c3 gnd f19 i/o k13 gnd p7 vcc v1 ch6n aa17 i/o c4 gnd f20 ioctrl k14 vcc p8 vcc v2 vccrec aa18 i/o c5 nc f21 i/o k15 vcc p9 gnd v3 vccrec aa19 i/o c6 i/o f22 ioctrl k16 nc p10 vcc v4 vccpll aa20 gndpll<1> c7 i/o g1 ch2p k17 i/o p11 gnd v5 gnd aa21 i/o c8 i/o g2 vccrec k18 i/o p12 vcc v6 nc aa22 i/o (sheet 1 of 2)
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 55 www.quicklogic.com c9 i/o g3 vccrec k19 i/o p13 vcc v7 clk<2>/pll in<2> ab1 gnd c10 i/o g4 gndpll k20 i/o p14 gnd v8 nc ab2 vcc c11 i/o g5 gnd k21 i/o p15 vcc v9 i/o ab3 i/o c12 inref g6 vcc k22 i/o p16 i/o v10 i/o ab4 i/o c13 i/o g7 gnd l1 clkap p17 i/o v11 i/o ab5 i/o c14 i/o g8 nc l2 vccrec p18 i/o v12 i/o ab6 i/o c15 i/o g9 clk<0> l3 vccrec p19 i/o v13 i/o ab7 i/o c16 i/o g10 nc l4 gndpll p20 i/o v14 i/o ab8 i/o c17 i/o g11 nc l5 gnd p21 i/o v15 i/o ab9 i/o c18 i/o g12 gnd l6 vcc p22 i/o v16 i/o ab10 i/o c19 i/o g13 nc l7 gnd r1 ch4p v17 nc ab11 i/o c20 gndpll <0> g14 nc l8 gnd r2 vccrec v18 nc ab12 i/o c21 i/o g15 i/o l9 gnd r3 vccrec v19 i/o ab13 i/o c22 i/o g16 gnd l10 gnd r4 gndpll v20 i/o ab14 i/o d1 ch1n g17 vccio l11 gnd r5 gnd v21 i/o ab15 i/o d2 vccrec g18 i/o l12 gnd r6 vcc v22 i/o ab16 i/o d3 vccrec g19 i/o l13 gnd r7 vcc w1 ch6p ab17 i/o d4 vccpll g20 i/o l14 vcc r8 gnd w2 vccrec ab18 i/o d5 nc g21 inref l15 vcc r9 vcc w3 vccrec ab19 i/o d6 nc g22 i/o l16 clk<6> r10 vcc w4 gndpll ab20 gnd d7 vcc h1 ch3n l17 vccio r11 gnd w5 nc ab21 vccpll<1> d8 tck h2 vccrec l18 i/o r12 vcc w6 trstb ab22 i/o d9 i/o h3 vccrec l19 clk<8> r13 vcc w7 clk<3>/pll in<1> d10 i/o h4 vccpll l20 i/o r14 vcc w8 clk<4> dedclk/pl lin<0> d11 i/o h5 gnd l21 i/o r15 gnd w9 i/o d12 i/o h6 vcc l22 i/o r16 nc w10 i/o d13 i/o h7 vcc m1 clkbn r17 vccio w11 i/o d14 i/o h8 gnd m2 vccrec r18 i/o w12 i/o d15 i/o h9 vcc m3 vccrec r19 i/o w13 i/o d16 i/o h10 vcc m4 vccpll r20 i/o w14 i/o table 44: 484 pbga pinout table pin function pin function pin function pin function pin function pin function (sheet 2 of 2)
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 56 516 pbga pinout diagram figure 61: ql82sd - 516pbga top view figure 62: ql82sd - 516pbga bottom view quicksd ql82sd-6pb516c a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 pin a1 corner
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 57 www.quicklogic.com 516 pbga pinout table table 45: 516 pbga pinout table pin function pin function pin function pin function pin function pin function a01 nc d09 io(c) h05 io(c) p01 io(d) w23 io(a) ac19 gndpll a02 io(c) d10 io(c) h06 vcc p02 ioctrl(d) w24 io(a) ac20 vccpll a03 io(c) d11 io(c) h21 vcc p03 inref(d) w25 io(a) ac21 gndpll a04 ioctrl(c) d12 io(c) h22 vcc p04 ioctrl(d) w26 io(a) ac22 gnd a05 io(c) d13 io(c) h23 pllrst(1) p05 io(d) y01 io(d) ac23 nc a06 io(c) d14 clk(5) h24 gnd p06 vccio(d) y02 io(d) ac24 gnd a07 io(c) d15 io(b) h25 io(b) p11 gnd y03 io(d) ac25 io(a) a08 io(c) d16 io(b) h26 io(b) p12 gnd y04 io(d) ac26 io(a) a09 io(c) d17 io(b) j01 io(d) p13 gnd y05 clk(1) ad01 io(d) a10 io(c) d18 io(b) j02 io(d) p14 gnd y06 vccio(d) ad02 tdi a11 io(c) d19 io(b) j03 io(c) p15 gnd y21 vccio(a) ad03 gnd a12 io(c) d20 io(b) j04 io(c) p16 gnd y22 clk(4)ded clk, pllin(0) ad04 vccrec a13 tms d21 io(b) j05 io(c) p21 vccio(a) y23 io(a) ad05 vccrec a14 clk(8) d22 io(b) j06 vccio(d) p22 ioctrl(a) y24 io(a) ad06 vccrec a15 io(b) d23 io(b) j21 vccio(a) p23 io(a) y25 io(a) ad07 vccrec a16 io(b) d24 io(b) j22 pllout(0) p24 ioctrl(a) y26 io(a) ad08 vccrec a17 io(b) d25 io(b) j23 io(b) p25 io(a) aa01 io(d) ad09 vccrec a18 io(b) d26 io(b) j24 io(b) p26 nc aa02 io(d) ad10 vccrec a19 io(b) e01 io(c) j25 io(b) r01 io(d) aa03 io(d) ad11 vccrec a20 io(b) e02 io(c) j26 io(a) r02 io(d) aa04 clk(0) ad12 vccrec a21 io(b) e03 io(c) k01 io(d) r03 io(d) aa05 gnd ad13 vccrec a22 io(b) e04 io(c) k02 io(d) r04 io(d) aa06 gnd ad14 vccrec a23 ioctrl(b) e05 io(c) k03 io(d) r05 vcc aa07 vcc ad15 vccrec a24 io(b) e06 io(c) k04 io(d) r06 vcc aa08 vcc ad16 vccrec a25 io(b) e07 inref(c) k05 io(c) r11 gnd aa09 vcc ad17 vccrec a26 io(b) e08 vcc k06 gnd r12 gnd aa10 vcc ad18 vccrec b01 io(c) e09 io(c) k21 gnd r13 gnd aa11 vcc ad19 vccrec b02 io(c) e10 io(c) k22 io(b) r14 gnd aa12 vcc ad20 vccrec b03 io(c) e11 io(c) k23 io(b) r15 gnd aa13 vcc ad21 vccrec b04 io(c) e12 vcc k24 io(b) r16 gnd aa14 vcc ad22 vccrec b05 io(c) e13 io(c) k25 io(a) r21 vcc aa15 vcc ad23 vccrec b06 io(c) e14 io(b) k26 io(a) r22 io(a) aa16 vcc ad24 gnd b07 io(c) e15 io(b) l01 io(d) r23 io(a) aa17 vcc ad25 clk(2) b08 io(c) e16 vcc l02 io(d) r24 io(a) aa18 vcc ad26 io(a) b09 io(c) e17 io(b) l03 io(d) r25 io(a) aa19 vcc ae01 tck b10 io(c) e18 io(b) l04 io(d) r26 inref(a) aa20 vcc ae02 tdo b11 io(c) e19 io(b) l05 vcc t01 io(d) aa21 gnd ae03 gnd b12 io(c) e20 io(b) l06 vcc t02 io(d) aa22 vcc ae04 vccrec b13 io(c) e21 io(b) l11 gnd t03 io(d) aa23 io(a) ae05 vccrec b14 clk(7) e22 io(b) l12 gnd t04 io(d) aa24 io(a) ae06 vccrec b15 io(b) e23 io(b) l13 gnd t05 io(d) aa25 io(a) ae07 vccrec b16 io(b) e24 io(b) l14 gnd t06 vcc aa26 io(a) ae08 vccrec b17 io(b) e25 io(b) l15 gnd t11 gnd ab01 io(d) ae09 vccrec b18 io(b) e26 io(b) l16 gnd t12 gnd ab02 io(d) ae10 vccrec b19 io(b) f01 vccpll(0) l21 vcc t13 gnd ab03 nc ae11 vccrec b20 io(b) f02 gndpll(0) l22 io(a) t14 gnd ab04 vcc ae12 vccrec b21 nc f03 io(c) l23 io(a) t15 gnd ab05 gnd ae13 vccrec b22 inref(b) f04 io(c) l24 io(a) t16 gnd ab06 gnd ae14 vccrec b23 io(b) f05 io(c) l25 io(a) t21 vcc ab07 gnd ae15 vccrec b24 io(b) f06 gnd l26 io(a) t22 vcc ab08 gnd ae16 vccrec b25 io(b) f07 vccio(c) m01 io(d) t23 io(a) ab09 gnd ae17 vccrec b26 io(b) f08 vcc m02 nc t24 io(a) ab10 gnd ae18 vccrec c01 io(c) f09 vccio(c) m03 io(d) t25 io(a) ab11 gnd ae19 vccrec c02 io(c) f10 gnd m04 io(d) t26 io(a) ab12 gnd ae20 vccrec (sheet 1 of 2)
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 58 c03 io(c) f11 vcc m05 io(d) u01 io(d) ab13 gnd ae21 vccrec c04 io(c) f12 vccio(c) m06 vccio(d) u02 io(d) ab14 gnd ae22 vccrec c05 ioctrl(c) f13 gnd m11 gnd u03 io(d) ab15 gnd ae23 vccrec c06 io(c) f14 vccio(b) m12 gnd u04 io(d) ab16 gnd ae24 gnd c07 io(c) f15 vcc m13 gnd u05 io(d) ab17 gnd ae25 gnd c08 io(c) f16 vcc m14 gnd u06 gnd ab18 gnd ae26 clk(3)plli n(1) c09 io(c) f17 gnd m15 gnd u21 gnd ab19 gnd af01 nc c10 io(c) f18 vccio(b) m16 gnd u22 io(a) ab20 gnd af02 nc c11 io(c) f19 vcc m21 vccio(a) u23 io(a) ab21 gnd af03 gnd c12 io(c) f20 vccio(b) m22 vcc u24 io(a) ab22 gnd af04 ch0n c13 io(c) f21 gnd m23 io(a) u25 io(a) ab23 trstb af05 ch0p c14 clk(6) f22 io(b) m24 io(a) u26 io(a) ab24 io(a) af06 ch1n c15 io(b) f23 io(b) m25 io(a) v01 nc ab25 io(a) af07 ch1p c16 io(b) f24 io(b) m26 io(a) v02 io(d) ab26 nc af08 ch2n c17 io(b) f25 io(b) n01 io(d) v03 io(d) ac01 io(d) af09 ch2p c18 io(b) f26 vccpll(1) n02 io(d) v04 io(d) ac02 io(d) af10 ch3n c19 io(b) g01 io(c) n03 io(d) v05 io(d) ac03 nc af11 ch3p c20 io(b) g02 gnd n04 io(d) v06 vccio(d) ac04 gnd af12 clkan c21 ioctrl(b) g03 pllout(1) n05 io(d) v21 vccio(a) ac05 gnd af13 clkap c22 io(b) g04 io(c) n06 gnd v22 io(a) ac06 vccpll af14 clkbn c23 io(b) g05 io(c) n11 gnd v23 io(a) ac07 gndpll af15 clkbp c24 io(b) g06 vccio(d) n12 gnd v24 nc ac08 vccpll af16 ch4n c25 io(b) g21 vccio(a) n13 gnd v25 io(a) ac09 gndpll af17 ch4p c26 io(b) g22 io(b) n14 gnd v26 io(a) ac10 vccpll af18 ch5n d01 io(c) g23 io(b) n15 gnd w01 io(d) ac11 gndpll af19 ch5p d02 io(c) g24 io(b) n16 gnd w02 io(d) ac12 vccpll af20 ch6n d03 io(c) g25 io(b) n21 gnd w03 io(d) ac13 gndpll af21 ch6p d04 io(c) g26 gndpll(1) n22 io(a) w04 nc ac14 vccpll af22 ch7n d05 io(c) h01 io(c) n23 io(a) w05 vcc ac15 gndpll af23 ch7p d06 io(c) h02 io(c) n24 io(a) w06 vcc ac16 vccpll af24 nc d07 io(c) h03 io(c) n25 io(a) w21 vcc ac17 gndpll af25 nc d08 io(c) h04 pllrst(0) n26 io(a) w22 io(a) ac18 vccpll af26 nc table 45: 516 pbga pinout table pin function pin function pin function pin function pin function pin function (sheet 2 of 2)
? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 59 www.quicklogic.com contact information telephone: 408 990 4000 (us) 416 497 8884 (canada) 44 1932 57 9011 (europe) 49 89 930 86 170 (germany) 852 8106 9091 (asia) 81 45 470 5525 (japan) e-mail: info@quicklogic.com support: support@quicklogic.com web site: http://www.quicklogic.com/ revision history copyright information copyright ? 2002 quicklogic corporation. all rights reserved. the information contained in this manual, and the accompanying software programs are protected by copyright-all rights are reserved by quicklogic corporation. quicklogic corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwise distributing any part of this product with- out the prior written consent of an authorized representative of quicklogic is prohibited. quicklogic ? , pasic ? , and vialink ? and quick works ? are registered trademarks of quicklogic corporation. verilog ? is a registered trademark of cadence design systems, inc. table 46: revision history revision date originator and comments rev. a - preliminary sept. 2001 first release - paul micallef and john kim rev. b - preliminary dec. 2001 changes to diagrams and data - paul micallef and john kim rev. c - preliminary june 2002 updated performance figures - paul micallef and john kim
www.quicklogic.com ? 2002 quicklogic corporation       ql82sd device data sheet rev c preliminary 60


▲Up To Search▲   

 
Price & Availability of QL82SD-PT280

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X